CANONIC SIGNED DIGIT ARITHMETIC The number of add operations required in a constant coefficient multiplication equals one less than the number of. Constant multiplication can be carried out efficiently using a canonical signed-drift (CSD) representation of the multiplier. With this method, the multipl. Abstract: This paper presents a novel high-speed binary CSD (BCSD) multiplier which takes advantage of the benefits coming from the canonic signed digit.

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### Canonical signed digit

The output of the second adder is passed to a fixed shift blockwhich applies a fixed shift of four bits to the right. The outputs of the first adder and canonical signed digit multiplier fixed shift block are passed to a third adderand the output of the third adder is supplied as a data output on the output line Thus, as required, the output of the first variable shift block 0 is shifted to the right by 0 bits or 1 bit; the output of the second variable shift block 1 is shifted to the right by 2 bits or 3 bits; the output of the third variable shift block 2 is shifted to the right by 4 bits or 5 bits by means of the variable shift block 2 and the fixed shift block ; and the output of the fourth variable shift block 3 is shifted to the right by 6 bits or 7 bits.

This structure has a lower truncation error than some conventional devices. However, in accordance with the invention, the truncation error can canonical signed digit multiplier reduced further. The input data values received on the data line are applied to respective first inputs of each of four multiplexers 0, 1.

A second input line carries all zeros, and the input data values received on the data line are also applied to an inverterwith the inverter output being applied on the inverse line to respective third inputs of the multiplexers 0, 1.

## USB2 - Canonical signed digit multiplier - Google Patents

The operation of the multiplexers 0, 1. However, in this case, the first variable shift block 0 can either shift the data to the left by three bits or by two bits, without truncation, the second variable shift block 1 can either shift the data to the left by one bit, without truncation, or can apply no bit shift, the third variable shift block 2 can canonical signed digit multiplier shift the data to the right by one bit canonical signed digit multiplier by two bits, and the fourth variable shift block 3 can either shift the data to the right by three bits or by four bits.

The fact that the first variable shift block 0 and the second variable shift block 1 canonical signed digit multiplier shift the data to the left, without truncation, improves the precision of the device, albeit at the cost of slightly more complex hardware.

No fixed shift is applied to the output of either the first adder or the second adder The outputs of the first adder and the second adder canonical signed digit multiplier passed to a third adderand the output of the third adder is supplied as a data output on the output line Thus, as required, the output of the first variable shift block 0 is shifted to the left by 3 bits or 2 bits; the output of the second variable shift block 1 is shifted to the left by 1 bits or 0 bits; the output of the third variable shift block 2 is canonical signed digit multiplier to the right by 1 bit or 2 bits; and the output of the fourth variable shift block 3 is shifted to the right by 3 bits or 4 bits.

However, in this case, the first variable shift block 0 can either shift the data to the left by three bits or by two bits, without truncation, the second variable shift block 1 can either shift the data to the left by one bit, without truncation, or can apply no bit shift, the third variable shift block 2 can either shift the data to the left by three bits or by two bits, without truncation, and the fourth variable shift block 3 can either shift the data to the left by one bit, without truncation, or can apply no bit shift.

Again, the fact that the first variable shift blocks 3 can shift the data to the left, without truncation, improves the precision of the device, albeit at the cost canonical signed digit multiplier slightly more complex hardware. No fixed shift is applied to the output of the first adderwhile the output of the second adder is applied to a fixed shift blockwhich applies a shift of 4 bits to the right.

Thus, as required, the output of the first variable shift block 0 is shifted to the left by 3 bits or 2 bits; the output of the second variable shift block 1 is shifted to the left by 1 bits or 0 bits; the output of the third variable shift block 2 is shifted to the right by 1 bit or 2 bits considering the effect of the third variable shift block 2 and the fixed shift block together ; and the output of the fourth variable shift block 3 is shifted to the right by 3 bits or canonical signed digit multiplier bits considering the effect of the fourth variable shift block 3 and the fixed shift block together.

It is also possible to use a structure which suffers from no truncation errors, again at a cost of slightly further increased hardware complexity, because the bit precision of the outputs must be increased.

## Math - What is a canonical signed digit? - Stack Overflow

No fixed shift is applied canonical signed digit multiplier the output of the second adderwhile the output of the first adder is applied to a fixed shift blockwhich applies a shift of 4 bits to the left.

Again, the fact canonical signed digit multiplier the variable shift blocks 3 and the fixed shift block can shift the data to the left, without truncation, improves the precision of the device, albeit at the cost of slightly more complex hardware.

The outputs of the second adder and the fixed canonical signed digit multiplier block are passed to a third adderand the output of the third adder is supplied as a data output on the output line Thus, as required, the output of the first variable shift block 0 is shifted to the left by 7 bits or 6 bits considering the effect of the first variable shift block 0 and the fixed shift block together ; the output of the second variable shift block 1 is shifted to the left by 5 bits or 4 bits considering the effect of the second variable shift block 1 and the fixed shift block together ; the output of the third variable shift block 2 is shifted to the left by 3 bits or 2 bits; and the output of the fourth variable shift block 3 is shifted to the left by canonical signed digit multiplier bit or has no bit shift applied.

There are thus described specific embodiments for multiplying data by any set of 8-bit constants, and it will be appreciated that the same principle can be applied to constants of any length.

When the multiplier is to be used with a set of constants that is known in advance, some simplifications can be made, since the multiplier may not need to be able to operate with some of the possible values.

Specifically, each pair of two consecutive bits i.

## Canonical signed digit - Wikipedia

For each canonical signed digit multiplier of n i. Then, again for each value of n, the listed values are examined, to determine whether any simplification of the corresponding multiplexer, shifter and adder can be made.

With regard to the multiplexer, it was mentioned above that there are five possible pairs of values for two consecutive bits. These can be canonical signed digit multiplier into three subsets: If the listed values come from two of the above subsets, the corresponding multiplexer is reduced from 3: If the listed values only come from subset0, the shifter can be removed.

With regard to the adder, then, if a shifter is removed as described above, the corresponding adder, that would have received one of its inputs from that shifter, can also be removed.